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| 1 features ? 4-port spacewire rout er with a system interface port for a total of 5 ports ? data rates up to 200mbps fu ll duplex on all 4 spacewire ports ? compliant to the spacewire standard, document number ecss-e-st-50-12c (http://www.ecss.nl/) ? group adaptive routing for 2 ports when using logical addressing ? replicated lookup tables for each receive port no arbitration is necessary when accessing lookup table data ? host (fifo) clock max frequency: 50mhz for 200mbps -9 by 128 receive and transmit fifos on each port ? non-blocking cross-point sw itch connecting any receive port to any transmit port ? path and logical addressing support ? internal status/error registers accessible via the configuration protocol ? routing is table accessible vi a the configuration protocol which holds the logical address to transmit port mapping ? any spacewire port can read or write to the configuration port, along with the host processor, by utilizing the configuration protocol ? internal control logic to support the operation of arbitration and group adaptive routing. (group adaptive routing for 2 ports) ? in external time-code in terface comprising tick_in, tick_out and curren t tick count value ? system interface features - low-power fifo memories - clocked push and pop interfaces - hard set full/almost full/empty/almost empty flags - spacewire in/out ports are c ontrolled by separate clock and enable signals. transmit fifo input port is controlled by a free-running clock (host_clk). ? cold spare on lvds pins ? 3.3v i/o supply (v dd ) ? 2.5v core supply (v ddc ) ? esd rating class 2 2000 v for lvds pins ? temperature range: -40c to +105c ? operational environment: - total-dose: 100 krad(si) - latchup immune (let >100 mev-cm 2 /mg) ? packaging options: - 255-lead clga - 255-lead cbga - 255-lead ccga ? standard microcircuit drawing 5962-08244 -qml q and q+ (pending) -qml v (pending) introduction the aeroflex ut200spw4rtr is a 4-port router capable of operating at data rates from 10 to 200 mbps. a parallel host interface is also provided for a total of 5 ports on the router. the router implements a non-blocking crosspoint switch and a "round robin" arbitration scheme allowing all 5 receive ports access to all 5 transmit ports. path and logical addressing are supported (per ecss-e-st-50- 12c) and lookup table storage is replicated 5 times giving each receive port a dedicated block of memory for logical addressing. configuration of lookup tables, as well as access to internal registers may occur through any of the 5 ports using a simple configuration protocol. a group adaptive function is also provided for 2 ports when implementing logical addressing. each of the four spacewire ports is capable of running at an independent speed. this allows for systems to be configured with nodes/instruments running at different speeds. if one node/instrument does not need to be sampled as often as another a more efficient power management scheme can be achieved. the physical interface can be either a lvds or lvcmos interface. this allows the user to select the interface that best meets system and reli ability requirements. the lvds interface can directly connect and drive up to 10 meters of cable. the lvcmos interface must inte rface to lvds drivers and receivers. independent look up table memo ry space is provided for each port. having separate look up tables reduces bottle necks by allowing each port access to a non shared lookup table. standard products ut200spw4rtr 4-port spacewire router preliminary datasheet april 26, 2011 www.aeroflex.com/spacewire
2 figure 1. ut200spw4r tr spacewire 4-port router block diagram aeroflex ut200spw4rtr 4 port spacewire router rd_logic_3 rd_logic_1 wr_logic_1 wr_logic_2 port 1 port 3 port 2 wr_logic_3 rd_logic_2 9 tx_data 9 tx_full tx_push write capable system receive fifo tx_fifo rx_fifo init tx_int rx_int aeroflex spacewire lph core rx_data rx_empty rx_pop tx_fifo rx_fifo init tx_int rx_int tx_fifo rx_fifo init tx_int rx_int look up table write look_up_1 ram block 8 we din look_up_ext ram block we din port_addr_1 port_addr_ext port_addr_2 configuration aeroflex spacewire lph core aeroflex spacewire lph core rd_logic_ext wr_logic_ext port_addr_3 rd_logic_4 wr_logic_4 port 4 tx_fifo rc_fifo init tx_int rc_int aeroflex spacewire lph core port_addr_4 system transmit fifo tx_afull rx_aempty read capable host_clk 8 time_code tick_out tick_in time code manager txclk_in_1 tx_div 5 arbiter arbiter arbiter arbiter arbiter tx1_d_lv phy interface lvds 2 tx1_s_lv 2 rx1_d_lv 2 rx1_s_lv 2 tx1_d tx1_s rx1_d rx1_s lvcmos tx2_d_lv phy interface lvds 2 tx2_s_lv 2 rx2_d_lv 2 rx2_s_lv 2 tx2_d tx2_s rx2_d rx2_s lvcmos tx3_d_lv phy interface lvds 2 tx3_s_lv 2 rx3_d_lv 2 rx3_s_lv 2 tx3_d tx3_s rx3_d rx3_s lvcmos tx4_d_lv phy interface lvds 2 tx4_s_lv 2 rx4_d_lv 2 rx4_s_lv 2 tx4_d tx4_s rx4_d rx4_s lvcmos txclk_in_2 txclk_in_3 txclk_in_4 3 applications information aeroflex colorado springs' ut200spw4rtr 4-port router offers a highly adaptable solution for a distributed network. the number of ports allows for a very reliable system where multi- ple nodes can be connected togeth er to gain performance. using the non-blocking cross-point switch the shortest path between nodes can be configured. each node can transmit and receive packets and each connection betw een nodes can carry multiple packets. the 4-port router is fu ll duplex on each of the ports. the router also allows for a sm all centralized network config- uration. 1.0 interfaces 1.1 spacewire the ut200spw4rtr 4-port router provides four ecss-e-st-50-12c compliant n ode interfaces. each node con- tains a transmit and receive fifo used to buffer data being sent within the network. the transmit fifo takes data from a host system and transmits it to a no de. where as the receive fifo accepts data from a node and passes it to the host system. a host system is what the node is co nnected to and can be a micropro- cessor, computer, sensor or memo ry unit and is responsible for data management. 1.1.1 port initialization all four ports follow the initialization procedure as defined in ecss-e-st-50-12c. following are the key components of the initialization process. after a reset or disconnect the link will initiate operation at a signaling rate of 10 mbps, 1 mbps. this provides the system with a common data rate while the system is checked for proper operation. once the operation of the system is validated each of th e four ports will switch to the specified transmit data rate. each of the four ports must be ca- pable of running at 10 1 mbps. 1.2 system interface the ut200spw4rtr 4-port router provides a system interface to the user in the form of receive and transmit fifo's. each fifo is 9 bits wide by 128 deep. data format for the fifo is 8-bits of data [7:0] and one bit [8] to indicate when an eop or an eep has been r eceived. a eop is an end-of- packet marker and is used to in dicate that a packet of data has been successfully sent. an eep is an error-end-of-packet and signals that there was an error with in the packet. table 1 shows the eop/eep handling. 1.2.1 system port transmit fifo the transmit fifo is write capab le by the user and is 9 bits wide by 128 deep. full (tx_full) and almost full (tx_afull) flags are provided to help the user prevent over- writing the fifo. data will be written into the fifo on the ris- ing edge of the clock when tx_push is ?low?. the levels of the almost full flags can not be changed by the user. 1.2.2 system port receive fifo a second 9 bit wide by 128 deep fifo is provided for the user interface to receive data. data received from one of the spacewire ports is read from th e receive fifo on the rising edge of the host clock when rx_pop is ?low?. this fifo is first byte fall through. 1.3 spacewire physical interface the ut200spw4rtr provides two different physical interfac- es to the user. the first is on chip lvds that can drive cable lengths up to 10 meters. the second is single ended lvcmos in the event the user wishes to use discrete lvds drivers and receivers. examples of these tw o configurations are shown in figures 4 and 5. in figure 5 th e external lvds devices are aeroflex quad drivers and receivers. table 1. eop an d eep handling 9-bit data character type 100000000 eop 100000001 eep figure 3. system receive interface 9 system receive fifo rx_data rx_empty rx_pop rx_aempty read capable host_clk figure 2. system transmit interface 9 tx_data tx_full tx_push write capable system transmit fifo tx_afull host_clk 4 tx1_d_lv tx1_s_lv rx1_d_lv 2 rx1_s_lv 2 tx1_d tx1_s rx1_d ut200spw4rtr 4 port spacewire router port 1 rx1_s 2 2 spacewire bus tx2_d_lv tx2_s_lv rx2_d_lv 2 rx2_s_lv 2 tx2_d tx2_s rx2_d rx2_s 2 2 tx3_d_lv tx3_s_lv rx3_d_lv 2 rx3_s_lv 2 tx3_d tx3_s rx3_d rx3_s 2 2 tx4_d_lv tx4_s_lv rx4_d_lv 2 rx4_s_lv 2 tx4_d tx4_s rx4_d rx4_s 2 2 spacewire bus lvds lvcmos port 2 lvds lvcmos port 3 lvds lvcmos port 4 lvds lvcmos spacewire bus spacewire bus figure 4. 4-port router on chip lvds interface 5 tx1_d_lv tx1_s_lv rx1_d_lv 2 rx1_s_lv 2 tx1_d tx1_s rx1_d ut200spw4rtr 4 port spacewire router port 1 rx1_s 2 2 ut54lvds031lv spacewire bus ut54lvds032lv tx2_d_lv tx2_s_lv rx2_d_lv 2 rx2_s_lv 2 tx2_d tx2_s rx2_d rx2_s 2 2 ut54lvds031lv spacewire bus ut54lvds032lv tx3_d_lv tx3_s_lv rx3_d_lv 2 rx3_s_lv 2 tx3_d tx3_s rx3_d rx3_s 2 2 ut54lvds031lv spacewire bus ut54lvds032lv tx4_d_lv tx4_s_lv rx4_d_lv 2 rx4_s_lv 2 tx4_d tx4_s rx4_d rx4_s 2 2 ut54lvds031lv spacewire bus ut54lvds032lv lvds lvcmos port 2 lvds lvcmos port 3 lvds lvcmos port 4 lvds lvcmos figure 5. 4-port router ex ternal lvds interface 6 1.4 power requirements the four-port router shall operate with a 2.5v co re voltage supply and an i/o supply set at 3.3v. 1.4.1 power sequencing to avoid large surge currents, v dd should be powered up either before v ddc or synchronously with v ddc (v dd > v ddc ). do not power up the core voltage supply v ddc before the i/o supply v dd ; doing so will cause a large in-rush current from v ddc to v dd that will stress the power supplies and router components. for prop er operation, connect all v dd pins to 3.3v, v ddc pins to 2.5v, and ground all vss pins (i.e., no floating v dd , v ddc , or v ss input power pins). if v dd and v ddc are being powered up synchronously ensure that the voltage difference between v ddc and v dd does not exceed 0.4v (v ddc - v dd < 0.4v). see ac electrical characteristics. 1.4.2 lvcmos i/o tie unused lvcmos inputs to v ss through a 1k ? to 10k ? resistor. it is good design practice to tie unused inputs to v ss via a resistor to reduce noise susceptibility. the resistor pro- tects the input pin by limiting the current from high going vari- ations in v ss which could damage the input to the device. unused lvcmos outputs can be left open. 1.4.3 lvds i/o all unused lvds receiver inputs an d driver outputs can be left open if not in use. no termin ation resistors are required across the differential lvds driver output pins. if the differential out- puts on the driver are shorte d together, there will be 0v between the 2 outputs. assuming that the outputs are only shorted to each other, no damage will occur. the output of the lvds drivers is a constant cu rrent source that delivers a nomi- nal current of ~3.5ma through the 100 ?? termination resistor. assuming that the outputs are shorted, the 3.5ma flows through the short between the outputs. if lvds receiver inputs are left floating, there is a fail safe mode on the receiver that will force the outputs to a high state. the receiver fail-safe conditions are: open input pins the unused inputs should be left open. do not tie unused receiver inputs to ground or a ny other voltages. this internal circuitry will guarantee a high, stable output state for open inputs. terminated input if the driver is disconnected (cable unplugged), or if the driver is in a three-state or poweroff condition, the receiver output will again be in a high state, even with the end of cable 100 ?? termination resistor across the input pins. shorted inputs if a fault condition occurs that shorts the receiver inputs together, thus resulting in a 0v differential input voltage, the receiver output remains in a high state. if both differential inputs are at v dd the output will be high. shorted input fail- safe is not supported across the common-mode range of the device (v ss to 2.4v). it is only supported with inputs shorted. table 2. power and ground pins pin name pin number description v dd t11, t5, n8, p11, n9, p14, n13, m7, k15, m10, j4, k3, j13, g3, h4, e7, h13, e10, g13, c11, g15, c14, d8, a5, d9, d13, a11 i/o and lvds supply voltage v ddc t8, r1, p8, n4, m15, l6, l11, k5, k12, h1, g5, g12, f6, f11, e15, d4, c8, b1, a8 core supply voltage v ss t1, n14, t14, l5, r8, l13, r11, l15, p3, j15, m1, h15, m5, f5, m8, f13, m9, f15, m12, d1 4, l7, l8, l9, l10, k6, k7, k8, k9, k10, k11,j1, j5, j6, j7, j8, j9, j10, j11, j12, h5, h6, h7, h8, h9, h10, h11, h12, g6, g7, g8, g9, g10, g11, f7, f8, f9, f10, e1, e5, e8, e9, e12, c3, b8, b11, a2, a14, r7, p5, p6, p7, p9, p10, n5, n6, n7, n10, n11, n12, m4, m6, m11, l4, k4, h2, g4, f4 i/o and core supply ground n/c p12, r14, p13, m13, l12, k13, f12, e11, e13, c10, c9, c7, l3, m3, n2, e4, e6, d5, d6, d7, d10, d11, d12, c12, c13, b14 no connect, pins must be left floating 7 1.5 clocks the ut200spw4rtr requires a transmit clock input for each of the ports. each of the ports is capable of running at an independent speed up to 200 mbps. separate external clock signals must be provided if each port is going to run at a different rate. if each spacewire port is going to run at a different rate tx_clk_in_1, tx_clk_in_2, tx_clk_in_3, tx_clk_in_4, as well as host_clk must be provided. each of the spacewire ports is cap able of running at an inde- pendent speed up to 200 mbps (200mhz clock). there is a one- to-one rule for the spacewire ports clocks. if port 1 is going to run at 160mbps a clock of 160mhz needs to be provided, 40mbps requires a 40 mhz clock, etc. the data values are transmitted directly and the strobe signal changes state whenever the data remains constant from one data bit interval to the next. the cloc k is recovered or extracted by xoring the data and strobe signal s. there is a slight delay be- tween edges of data/strobe, and the recovered clock. ds en- coding allows for the spacewire port speeds to have same transmit clock speed and offers good jitter tolerance, but the re- ceiver data is asynchronous to local (transmit) clock, refer to ecss-e-st-50-12c. the host_clk is used for the fi fo interface and also by the routing circuitry. the maximum host_clk frequency is 50mhz. host_clk frequency requirements are based on the fastest spacewire port data rate. th ere is a division by four rule that applies to host_clk and the output ports of the router. if one port of the router is co nfigured to run at 200mbps, host_clk must run at 50mhz. and if the maximum output frequency of one of the spacewire ports is 100mbps host_clk only needs to run at 25mhz. the clock require- ments for the 4-port router are shown in table 4. jitter on the input clocks must be minimized in order to reduce the cumulative effect on the data-strobe skew. jitter on the tx_clk_in_n input clocks dir ectly affects the data-strobe outputs. an unstable clock e dge will skew the data-strobe alignment. jitter must be accounted for in the system skew bud- get calculations. it is recommended that the rate at which a spacewire link trans- mits and receives speeds are with in 10x each other. meaning if the ut200spw4rtr is transmitt ing at 100mbps, the receive side should be no less than 10mbps. 1.5.1 initialization and link run data rates the spacewire standard requires an initialization data rate of 10mbps, this provides the system with a common data rate while it is checked for proper operation.the tx_div[4:0] in- put signals are used to load clock divide registers for the 10mbps initialization data rate requirement. once initialization is complete the data rate may go to the maximum specified by the user up to the maximum capability of the device. the user must know what divisi on factor is needed for each port to di- vide down to 10mbps. table 3: clock signals signal i/o description tx_clk_in_1 i transmit clock for port 1. max of 200 mhz tx_clk_in_2 i transmit clock for port 2. max of 200 mhz tx_clk_in_3 i transmit clock for port 3. max of 200 mhz tx_clk_in_4 i transmit clock for port 4. max of 200 mhz host_clk i used for all internal router func tions and to read and write to/ from the external fifo?s and the spacewire fifo?s tx_div[4:0] i input clock divide for the initial 10 mbps data rate 8 2.0 router architecture the ut200spw4rtr router is a modular design consisting of four major blocks with desc riptions of each as follows. 2.1 spacewire link protocol handlers there are four identical link pr otocol handler (lph) modules in the router. each lph consis ts of a transmit fifo, a receive fifo, receiver, transmitter a nd initialization block. all of these blocks combined are designed to handle the spacewire serial protocol as defined in document number ecss-e-st-50- 12c. 2.2 read logic block there is a read logic block co nnected to all four of the receive fifo's and the system interface transmit fifo. this block monitors the empty flag on the receive fifo and reads a byte of data whenever the fifo is not empty. this block also checks the first byte of data read after an eop to determine the port address or whether a c onfiguration transaction will be initiated. a configuration transaction is described later in this document. for path or logical addressing, the read logic block uses the first byte of data after an eop/eep. example: if the first byte of data after an eop/eep is between 0x20 and 0xff. the read logic block uses the data as an address for the lookup table. the data stored in the lookup table will be used as the port address. the fi rst byte of data wi th value 0x00 received by any router port after reset or an eop/eep will initiate a con- figuration transaction. if the fi rst byte after an eop/eep is be- tween 0x01 and 0x05 path addressing will be used. 2.3 write logic block the write logic blocks control the data to the transmit fifos and the system receive port (shown in figure 3). a "round robin" arbiter manages access and makes sure only one read logic block accesse s the write logic block. if more than one receive ports is waiting to send data out of the same output port a round-robin arbitration scheme has been im- plemented. it is also important to note that the configuration block will be accessing the write logic bloc k when read configuration packets are requested. in this case, the configuration block is treated as another read logic block. 2.3.1 arbitration each transmit fifo (tx_fifo in figure 6.) write logic block contains an arbiter that manages the flow of data to each of the four physical interface ports and the system receive port. the arbiter is a "round robin" type and gives each receive port equal opportunity for access. the arbiter starts counting whenever a request for that port is received from any of the five receive ports. the count is from port 1, port 2, etc. until the count reaches port 5, looks for configuration com- mands, and then starts over. example: if a transmit port (this is any of the physical ports or the user interface port) receives a request, for example, from port 1 and port 5 at the same time, the port 1 packet will be sent first. if during the time port 1 packet is se nt and a packet from port 3 is requested, the port 3 packet will be sent before port 5 because of the way the arbiter counts. 2.4 configuration the configuration block is used to set up lookup tables as well as registers that control the ope ration of the router. in addition, status registers and commands are accessed through this block. figure 6. spacewire lph module read logic tx_fifo rx_fifo init tx_int rx_int aeroflex spacewire lph core to/from physical interface write logic arbiter 9 3.0 general operation the ecss-e-st-50-12c defines two types of characters, data and control characters. these ch aracters are then further de- fined as either link characters or normal characters. a link char- acter does not get passed from th e exchange level to the packet level. some examples of a link character are flow control to- kens (fct), escape (esc), null control code (esc + fct), and the time-codes (esc + data character). a normal charac- ter ends with an eop or eep and is passed through the router at a packet level. 3.1 data character data characters hold an eight-bi t data value, transmitted least significant bit (lsb) to most significant bit (msb). a data character contains a parity bit, data-control flag, and eight bits of data. per ecss-e-st-50-1 2c data parity is odd. the parity bit will be calculated by adding the number of ones that are contained in the previous 8-bits of data. if the number of 1's in bits added together is even, the data character is said to have even parity. the data-control flag is set to zero to indicate that the current character is a data character. th e following fig- ure shows the 10-bit data character field. the lsb bit "p" is the parity bit, bit "dc" is the data-control flag and must be set to zero for data, and bits "d0 to d7" is the data. the parity bit covers the previous eight bits of a data character or two bits of a control character , the current parity bit and the current data-control flag. the parity bit is implemented in each data or control character to ai d in detection of transmission errors. 3.2 control character a control character is made up of a parity bit, data-control flag and two control bits. the data control flag is set to one to indi- cate that the current character is a control charact er. parity cov- erage is similar to that for a data character. one of the four possible control characters is the escape code (esc). this can be used to form control codes. two control codes are specified and valid which are the null c ode and the time-code. the lsb of the control character is the parity bit "p", bit "dc" is the data control bit and should be set to one for control, and bits "c0 and c1" are the control codes. refer to eccs-e-st-50- 12c section 7.3 for further deta ils. the control codes are de- fined in table 4. p dc c 0 c 1 p dc c 0 c 1 figure 8. control characters p dc d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 figure 7a. data character p 0 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 p 1 0 1 p 1 0 0 parity coverage flow control token end of packet data character figure 7b. parity coverage 10 3.3 sending packets the first byte of data received on the bus after power up or after an eop/eep is the header byte . the eop/eep are treated the same by the router. the header byte determines whether path addressing (0x01 to 0x05), logical addressing(0x20 to 0xff), or a configuration transaction 0x00 occur. if no configuration write transaction had occurred path addressing will be support- ed. path addressing will be used because the lookup tables have not yet been configured. currently, there is no re- striction on the size of the packet s that can be sent through the router. 3.4 bad packet packets that do not have a valid "path address" or do not have a look up table location configur ed are considered bad packets. bad packets can be read from the receive fifo, but not sent to any of the transmit fifos. this is commonly known as "spilling the packet". the router supports path address from 1 to 5 (physical output ports on the router) and logical address from 32 to 255, figure 5. table 4. control character table control character definition character type c0:c1 fct flow control token link 00 eop end of packet normal 01 eep error end of packet normal 10 esc escape link 11 table 5. bad add ress identification bad address description 0x06 to 0x1f the 4-port router has 4 spacewire ports and one external port for a total of 5 ports that will be supported using path addressing 0x20 to 0xff that contain a value of 0x00 look up tables will not be reset. any unused logical addresses should be set to contain hex 0x00. 11 4.0 configuration protocol the ut200spw4rtr 4-port router is configured through any one of the four spacewire ports or the external port. the de- fault configuration is for all ports to be configuration ports. if one or more ports are set up to be configuration ports only one configuration command can be sent at a time. 4.1 configuration ports if multiple ports are set up as configuration ports and more than one configuration command is being sent within the router the configuration packets will be corrupted. the first byte of data with value 0x00 received by any router port after reset or an eop/eep will initiate a configuration transaction. (ecss-e- st-50-12c). configuration transactions allow access to the lookup tables, configuration registers and status registers. the packet pr otocols for configuration reads and writes are specified in the following two sections. 4.2 configuration write a configuration write packet loads a 16-bit data word to the specified 16-bit address location in the configuration memory space. a configuration write pack et begins with zero (0x00) or can contain additional router addr ess bytes, followed the final destination address byte set to zero. a configuration write packet is shown in figure 9. next, the router id byte should be set to the value in the receiv- ing router id register. the pack et type byte should be set to write (see table 6.), followed by the address least significant byte, the address most significan t byte, then the data least sig- nificant byte and the data most significant byte. the last byte before the end of packet (eop) will be the arith- metic checksum value, which is an arithmetic sum of the final destination address, the router id, the packet type, the address and data bytes. if the checksu m value does not match, the com- mand will not be executed. if the packet has less than eight (8) bytes or the checksum value is not the last byte, the command will not be executed. (ecss-e-st-50-12c). 4.3 configuration read the read packet will read a number (count) of 8-bit data val- ues from consecutive 16-bit addr ess locations and transmit the data to the return location speci fied. this packet begins with zero or more hardware or logical address bytes followed by the final destination address byte set to zero. next, the router id byte should be set to the value in the router id register, unless the router id is being read. the packet type byte should be set to read, (0x01 or 0x02) followed by the ad- dress least significant byte, the address most significant byte, figure 11. configuration po rt read packet response 0 0x00 router id packet type address msb data lsb check sum eop check sum coverage protocol id or more address bytes address lsb data msb figure 9. configuration po rt write packet command router id packet type address lsb address msb count check sum eop check sum coverage 0 or more address bytes protocol id 1 or more return address bytes 0x00 figure 10. configuration po rt read packet command router id packet type address lsb address msb 1 or more data byte pairs (lsb-msb) check sum eop check sum coverage protocol id 0 or more address bytes 12 the word count byte, and one or more return path address byte(s). the order of the return pa th address bytes are to read in the order they are received. that is to say, the first return path address byte will be the path out of the first router with subsequent bytes to be used for the next layers of routers. the last byte will be the checksu m value, which is an arithmetic sum of the destination address, router id, packet type, address bytes, data bytes and return path bytes. if the checksum received does not match the calculated value, an error end of packet will be sent to the return address. the word count byte must be greater than zero. a value of zero will cause the command to not be exec uted. the return address path must contain one or more bytes and the first header byte must not be zero; otherwise the command will be considered invalid and not be executed. figure 10 shows the bytes required for a read packet command. 4.3.1 read no clear packet type a read no clear packet type will read the data as requested in by the read request packet. 4.3.2 read clear packet type the read clear packet type will read the data in the requested address space and delete the information contained there. 4.4 configuration read response the read response will follow the protocol shown in figure 11 a read response will be sent b ack to the requesting address after a read command is executed. the read packet command as shown in figure 5 sets up the address to read data from (address lsb/msb), how many 8-bit values to read (count), and the re- turn address bytes path. after the read command is executed a read response command will be issued and will contain the data byte pairs read from the specified address. 4.5 packet type byte definition the various configuration protocols define a "packet type" byte. this byte tells the router or the user in the case of the read response type what type of tran saction is being commanded or received. table 6 defines th e different packet types. table 6. packet type definitions packet type value (hex) write 0x00 read no clear 0x01 read clear 0x02 read response 0x03 reserved 0x04-0xff 13 5.0 port addressing 5.1 path addressing for any byte received immediat ely after an eop/eep byte with the value 0x01 to 0x05, path addressing will be implemented. addresses from 0x06 to 0x1f will be spilled. the entire port ad- dress space is defined in table 13. 5.2 logical addressing there are 4 lookup tables (one fo r each port) on the router. each lookup table is 224 by 16 and all 4 lookup tables have the same data written into them using the configuration protocol. a sin- gle configuration write will load each of the lookup tables with identical data the format for the lookup table data is described in the following sections. 5.2.1 lookup table data format the lookup tables on the router are organized into 16-bits and are organized as shown in table 7 below. 5.2.2 primary logical address bits the five lsb bits [4:0] are th e primary logical address bits and are for selecting ports 1 through 4 regardless of whether group adaptive has been enabled or not. when group adap- tive has been enabled the router looks at the port address spec- ified by these bits first and if that port is busy will then look at the port specified by the group adaptive address bits. 5.2.3 group adaptive address bits bits [9:5] are used when gro up adaptive has been enabled and the port selected by the primary logical address bits is busy. if group adaptive routing is not enabled and port selected by the primary logical address bits is busy the packet will have to wait until the selected port is free. 5.2.4 enable header delete bit bit [10] is used to enable the header delete function for the port selected by either the group ad aptive address bits or the pri- mary logical address bits. whenever this bit is set high the router will delete the header be fore sending the packet out of the requested transmit port. 5.2.5 enable group adaptive bit bit [11] is used to enable the group adaptive function on the router. setting this bit high tells the router to use bits [9:5] for the port select in the event the port select for the primary ad- dress bits is busy. 5.2.6 unused bits look up table bits [14:12] need to be set to 0x00. in order for the parity bit to be correct all th ree unused bits need to contain 0?s. if these bits are set to something other than 0x00 the parity calculation it will not be the same as what the router is calculat- ing. 5.2.7 parity bit a parity bit is included for each lookup table location. the par- ity is even. when the header by te is decoded and falls between address 0x20 and 0xff, a lookup table address will be retrieved by the lookup table. again, parity will be calculated by adding the number of ones that are contained in the previous 8-bits data. if the total number of 1's in bits added together is odd, the parity is odd parity. and if the number of 1's in bits added is even it is said to have even parity. the current parity bit wi ll then be compared to the cal- culated parity and if they are no t the same, the packet will be read out of the receive fifo. th is is commonly referred to as "spilling the packet". additionally, the parity error register will be incremented. parity error register is differen t from the previously discusses spacewire parity. the parity error register is based on the data in the lookup table. unused 15 14 13 11 enable group adaptive 10 enable header delete 9 8 7 6 5 group adaptive address bits 4 3 2 1 0 primary logical address bits parity 12 table 7. lookup table data format 14 6.0 configuration and status registers the router has a number of conf iguration and status registers which are used for initi al setup of the router and for monitoring the router's performance. table 14 is a summary of all the router registers with detailed descriptions outlined in each subsection. 6.1 router identification register the router identificat ion register is acces sed through config- uration address 0x0100 in hex. th e router id defaults to 0x00 upon reset and the user can writ e an 8-bit value using the con- figuration write protocol and using 00 for the router id byte in the protocol. configuring the router id register allows multiple routers to be networked together. assuming each router has unique identifi- er, the router id bits used in the configuration protocol will al- low each individual ro uter on the network, to have different look up table. 6.2 version this read only register located at address 0x0101 will tell the user what version of the router is being accessed. 6.3 configure port enable at power up, by default all of the ports on the router can be used as configuration ports. a read and write register at address 0x0101allows the user the abilit y to specify certain ports as configuration ports. refer to table 8 for the bit mapping for this register. 6.4 link run register address 0x0103 indicates to the user which ports are in the run state. bit 0 is for port 1 and bit 4 is for the external port. table 9. link run register 6.5 transmit full register address 0x0104 indicates to the user which transmit port fifo's are full. bit 0 is for port 1 and bit 4 is for the external port. 6.6 router error count address 0x0105 manages error co unting. the port has an error counter that is 4-bits wide. refer to table 10 for the bit assign- ments for each error counter. 6.7 parity error register any time a parity error is det ected during a lookup table access register 0x0106 will get written to . data is formatted as follows. bit 3 indicates whether there ha s been a parity error during a receive transaction. bits 4 to 0 indicate which receive port the error occurred on. 6.8 link disable register all ports on the router can be enabled or disabled by writing into register 0x0107. writing the appropriate bit in the link disable register will disable that port. refer to table 11 for the bit assignments. table 8. configure port enable address bit number description and comments low high 0x0101 0 disable port 1 enable port 1 1 disable port 2 enable port 2 2 disable port 3 enable port 3 3 disable port 4 enable port 4 4 disable external enable external address bit number port number 0x0103 0 1 1 2 2 3 3 4 4 external table 10. router error count registers address hex range error counter 0x0105 [3:0] port 1 [7:4] port 2 [11:8] port 3 [15:9] port 4 table 11. link disable register address bit number description and comments high low 0x0107 0 disable port 1 enable port 1 1 disable port 2 enable port 2 2 disable port 3 enable port 3 3 disable port 4 enable port 4 15 6.9 port busy registers registers 0x0109 to 0x010d are to indicate which transmit port has busy administering a receive por t. the three bit data field is used to indicate which transmit po rt is connected to the desired receive port. 6.10 time master register the time code master register, 0x010e, is used to tell the router which port is connected to the time master of the net- work. the default is port 5, the external port. 6.11 initialization divide registers used to set the correct 10mbps transmit data rate during initial- ization. value stored in registers 0x010f, 0x0110, 0x0111, and 0x0112 are 5-bit registers are used to divide the tx_clk thus deriving the 10mbps clock. on power up or reset the router will load the tx_div[4:0] bits into all 4 registers. the port that will be used to configure the router wi ll have to have the correct val- ue set by tx_div. example: if the user wishes to configure the router through port 3 and the transmit speed will be 100mbps the user will need to set tx_div to 0x0a or 10 in decimal. port 3 will have the correct divider for the 10mbps clock and will be able to ini- tialize the spacewire link. if the other ports are transmitting at different data rates the 10mbps initialization data rate will not be correct. the user will then use port 3 to set the transmit 10mbps register such that the initialization data rate will be 10mbps. table 13 shows some common data rates along with the correct register value to achieve the 10mbps initialization data rate. it is important to note that if tx_clk is set to less than 10mbps the initialization divide register must be set to 0x01. the 4-port router will be able to initialize at these data rates. the user needs to be aware howe ver to be careful not to send any data until the links are in th e run state. if the initialization data rates are different, one side of the link could reach the run state before the other and if that link begins to send data there is a good possibility the other side will disconnect because it re- ceived a normal character be fore reaching the run state. 6.12 router reset a write command to the address 0x0114 will reset the router with exception to the look up tabl es. spacewire ports are not re- set, only the router which include s the state machines used to select ports and read and write to fifo's. 6.13 receive fifo reset writing to address 0x0115 and setting any or all of the 5 bits will reset the appropriate recei ve fifo. for example, setting bit 0 will reset the receive fifo of port 1. setting bit 1 will re- set the port 2 receive fifo and so on. 6.14 transmit fifo reset this 5-bit register at address 0x0116 is used to reset any or all of the transmit fifos. bit 0 will reset port 1, bit 1 will reset port 2 and so on. table 12. clock settings and unit data rate tx_clk (mbps) tx_div[4:0] (hex) initialization data rate (mbps) 200 0x14 10 150 0x0f 10 10 0x01 10 5 0x01 5 table 13. header byte memory map port address byte (hex) port 0x00 configuration access 0x01 path address for port 1 0x02 path address for port 2 0x03 path address for port 3 0x04 path address for port 4 0x05 path address for port 5 0x06 to 0x1f not used 0x20 to 0xff logical address locations 16 table 14: configuration and status registers address (hex) r/w name default (hex) description number bits 0x0020- 0x00ff r/w lookup table xxxx logical address lookup table. look up tables are not reset. user should initialize the unused addresses to 0x00. 0x0100 r/w router id 0000 router identification register 8 0x0101 r version register 0001 router version register 0x0102 r/w configure port enable 001f using this register, ports can be enabled or disabled as configuration ports. 5 0x0103 r link run register 0000 indicates which ports are in the run state. one bit for each port 5 0x0104 r transmit full register 0000 transmit fifo full register. indicates which transmit fifo's are full, one bit for each transmit fifo 5 0x0105 r/rc router error count 0000 router error count regi sters. each nibble within this register represents the spacewire error count for a given router port. 0x0106 r/rc parity error register 0000 indicates when a parity error has occurred and the receive port number that last showed an error 6 0x0107 r/w link disable register 0000 enables or disables individual links 6 0x0108 r/w reserved 0000 0x0109 to 0x010d r port busy registers 00 these registers in dicate the current receive port to tran smit port connection. address 0109 is for receive port 1 and address 010d is for the external port 5 0x010e r/w time master select register 0005 this register is used to tell the router which port is connected to the time master 5 0x010f r/w port 1 initialization divide register tx_div port 1 10mbps data rate divider 5 0x0110 r/w port 2 initialization divide register tx_div port 2 10mbps data rate divider 5 0x0111 r/w port 3 initialization divide register tx_div port 3 10mbps data rate divider 5 0x0112 r/w port 4 initialization divide register tx_div port 4 10mbps data rate divider 5 0x0113 r/w protocol id 0000 programmable protocol identifier 0x0114 w router reset n/a a write command to this address will reset the entire router. the data in this case is don't care 5 0x0115 w receive fifo reset n/a used to reset any or all of the receive fifo's 5 0x0116 w transmit fifo reset n/a used to reset any or all of the transmit fifo's 17 7.0 time codes time codes are handled as they are described in the standard. a time code distributes system time over a network. a time code does not get saved into the fifo memory buffer. any valid time code received on a router port will be sent to all of the oth- er ports of the router. a valid time code is defined as a time code value that is one greater than the previous time code value. a time code is made up of an esc character followed by eight bit data character. the data char acter holds six bits of system time and two reserved bits. bits "t0 to t5" are the 6-bit time counter and are the lsb of the time code. bits "t6 to t7" are the timing control flags (currently reserved by the working group) and should both be set to zero. figure 12 illustrates a time-code packet 7.1 system time management the timing of the system is controlled by two signals, tick_in and tick_out. tick_in and tick_out are the system time controllers is the external port is the time master. when a tick_in is received it tells the node to send a time code character. only one node in the system should have an active tick_in and that node will pr ovide the master time reference for the entire network. then tick_out is asserted it tells the user that a valid time code character has been received. 7.2 transmit time the transmitter encodes data and transmits it through the net- work using ds encodi ng. the transmitter mu st receive either a time-code, flow control token (f ct), or an n-char (data, eop or eep) to initiate a transmit tran saction. if the transmitter does not have any data to send it will send null characters. the transmitter sends n-chars if the node at the other end of the link has room in the receive fifo buffer. a transmit transaction is initiated by the node at the end of the link sending a fct, this tells the transmitter that the node that it is ready to accept anoth- er 8 n-chars. the transmitter k eeps track of the fcts received and the number of n-chars sent to avoid input buffer overflow. this is done by the transmitter holding a credit count of the number of characters it has been given permission to send. 7.3 time code latency spacewire system time accuracy is dependent on the number of links traversed and th e operating speed of each link. a delay ap- proximately 14 bit periods (esc + data character) is added to the system time for each link the time code traverses. time code skew across a network is equal to ttcskew = (14*s)/a where s is the number of spacewire links traversed, a is the average link operating speed, and 14 is the time code bit period. 7.4 transmitter status the transmitter can be in one of four states: reset: the transmitter does nothing. send nulls: transmitter will only send nulls out on the link. no n-chars are read in fr om the transmit host interface. transmitter will not accep t an order to send fct from the host system. it does not send time-codes. send fcts or nulls: transmitter can send flow control to- kens or nulls, but still does not read n-chars from the trans- mit host interface. it do es not send time-codes. send time-codes, fcts, n-char s or nulls: normal system operation. transmitter is sending nulls, fcts, time-codes and n-chars. t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 p 1 1 t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 p 1 1 p 1 1 p 1 1 p 1 1 1 1 0 figure 12. time code 18 8.0 control signals 8.1 lv_cm allows the user to select the ex ternal interface either lvds or lvcmos. when lv_cm is high the lvds interface will be active. for example signal i/o that will be active are tx1_d_lv[1:0], tx1_s_lv[1:0], rx1_d_lv[1:0], and rx1_s_lv[1:0]. while tx1_d, tx1_s, rx1_d, and rx1_s would be tri-stated. table 15 shows the relationship between lv_cm and the transmit receive interface. 8.2 oe this signal is used to control the outputs of the receive fifo. oe supports the memory interface ti ming of host controller that incorporates multiple xed address and data on the bus. if no oe signal is available for the host controller, and the csel signal is asserted while the controller still has its address information on the bus, data may be driven onto the bus and cause bus con- tention. 8.3 csel allows the state of th e control signals for fifos to be connect- ed to internal rout er logic. if csel is "high" the signals tx_push , rx_pop , and any other backend inputs should not be allowed to be passed on to internal logic. additionally, out- put signals rx_data and time_code[7:0] should be tri- stated. see table 16. it should be noted that tick_in and tick_out are indepen- dent of the states of output enable (oe ), chip select (csel ), re- set (rst ). and the time code (time_code[7:0]) port will come up as an input port because the default time master is the external port. table 15. control signals lv_cm tx#_d_lv/tx#_s_lv rx#_d_lv/rx#_s_lv (lvcmos) tx#_d/tx#_s rx#_d/rx#_s (lvds) 1 z active 0 active z table 16. enable and select signals truth table oe csel rst time_code[7:0] rx_data[8:0] tx_push rx_pop 1 1 1 active z inactive 1 1 0 z z inactive 1 0 1 active z active 1 0 0 z z inactive 0 1 1 active z inactive 0 1 0 z z inactive 0 0 1 active active active 0 0 0 z z inactive 19 9.0 service configuration there are a few different ways that the ut200spw4rtr can be configured to service multiple system requirements 9.1 stand alone router the router can be used as a sta nd-alone router with up to four spacewire links connected to it, figure 13. configuration of the lookup tables should be done by sending packets containing configuration commands. 9.2 interfacing multiple routers network topology may require a router with more than four spacewire ports or more system por ts. multiple f our port rout- ers can be interfaced together in numerous conf igurations to produce the required i/o count. routers can be connected together via the system ports to ex- pand to an 8-port router. external logic will be required to con- nect the system ports together in this way. the router id register for each of the routers connected in this way should be unique. an extra path addressing byte will be needed to route packets between the routers connected through the system ports. three routers can be connected to a fpga or processor through the system port and to each ot her through the spacewire ports. this configuration generates eight spacewire ports for connec- tion to spacewire nodes. the syst em ports of each router are used to connect to user l ogic in an fpga or processor. spw node 2 spw node 3 processor 4 port router 1 2 3 4 5 spw node 1 figure 13. stand alone router configuration 4 port router 1 2 3 4 5 4 port router 1 2 3 4 5 control logic figure 14. 8-port ex tended configuration using external logic 4 port router 1 2 3 4 5 4 port router 1 2 3 4 5 4 port router 1 2 3 4 5 processor figure 15. 8-port extended configuration using up 20 10.0 networking many network configurations are possible using the 4-port router. certain parameters need to be considered when choos- ing a network topology to use. performance, fault-tolerance, and harness mass, are key attrib utes a designer must consider when designing a spw network. 10.1 centralized networks in a centralized network config uration all communications are routed by a router at the center of the network. allows certain functions are handled by the rout er, resulting in high perfor- mance. if a failure occurs on one node, other nodes are not af- fected. centralized networks ar e simple to configure because the look up tables do not need to be configured. data can be eas- ily accessed from all nodes via the central router. centraliza- tion's weaknesses is the heavy re liance on the central router and the high harness mass required. 10.2 distributed networks distributed network configurati ons are characterized by small- er routers all connected togeth er. many configurations are pos- sible, allowing for a more reli able system. all nodes on the network are connected together through some route. data can be accessed from all nodes but a path must be specified for how to route the data through the network. distributed networks are more complex to configure becau se the lookup tables usually need to be configured resulting in slower performance. figure 16. centralized network example spw node 2 spw node 4 spw node 3 processor 4 port router 1 2 3 4 5 spw node 1 4 port router 1 2 3 4 5 4 port router 1 2 3 4 5 4 port router 1 2 3 4 5 4 port router 1 2 3 4 5 4 port router 1 2 3 4 5 4 port router 1 2 3 4 5 4 port router 1 2 3 4 5 4 port router 1 2 3 4 5 4 port router 1 2 3 4 5 processor figure 17a. distributed network example #1 4 port router 2 4 port router 0 4 port router 1 4 port router 4 4 port router 5 4 port router 3 figure 17b. distributed network example #2 21 11.0 255-lead clga pin out vss time_code0 time_code2 time_code1 vdd tick_in tick_out vddc tx2_d tx2_s vdd tx1_d tx1_s vss tx1_d_lv- rx1_d_lv- vddc time_code3 time_code5 time_code4 time_code6 time_code7 vss vss rx2_d rx2_s vss rx1_d rx1_s nc tx1_d_lv+ rx1_d_lv+ tx_clk_in_1 tx_clk_in_2 tx_clk_in_3 vss vss vss vss vddc vss vss vdd nc nc vdd tx1_s_lv- rx1_s_lv- host_clk nc vddc tx_clk_in_4 vss vss vss vdd vdd vss vss vss vdd vss tx1_s_lv+ rx1_s_lv+ vddc rx2_d_lv- vss rx2_d_lv+ vdd rx2_s_lv- vss rxs_s_lv+ vss rx3_d_lv- vdd rx3_d_lv+ vss rx3_s_lv- vddc rx3_s_lv+ tx4_d_lv- rx4_d_lv- tx4_d_lv+ rx4_d_lv+ tx4_s_lv- rx4_s_lv- tx4_s_lv+ rx4_s_lv+ vss tx_div0 vss nc vss vss vdd vss vss vdd vss vss nc tx2_d_lv- csel tx_div1 vss nc vss vddc vss vss vss vss vddc nc vss tx2_d_lv+ oe tx_div2 vss vdd vddc vss vss vss vss vss vss vddc nc tx2_s_lv- vss lv_cm vdd tx_div3 vss vss vss vss vss vss vss vss vdd tx2_s_lv+ vddc vss vdd tx_div4 vss vss vss vss vss vss vss vss vdd tx3_d_lv- tx_data3 tx_data8 vss vdd vddc vss vss vss vss vss vss vddc vdd tx3_d_lv+ tx_data2 tx_data7 vss tx_afull vss vddc vss vss vss vss vddc nc vss tx3_s_lv- vss tx_data6 nc tx_full vss nc vdd vss vss vdd nc vss nc tx3_s_lv+ ts_data1 tx_data5 vddc tx_push nc nc nc vdd vdd nc nc nc vdd vss tx_data0 tx_data4 rx_pop vss rx_empty rx_aempty nc vddc nc nc vdd nc nc vdd vddc rst rx_data5 rx_data4 rx_data6 rx_data7 rx_data8 vss rx3_d rx3_s vss rx4_d rx4_s nc vss rx_data1 rx_data0 vdd rx_data2 rx_data3 vddc tx3_d tx3_s vdd tx4_d tx4_s vss t r p n m l k j h g f e d c b a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 22 12.0 pin descriptions system pins pin no. pin name i/o type description v ddc pwr power core power supply 2.5v v dd pwr power i/o power supply3.3v gnd pwr power ground vss n1 host_clk i lvcmos 50mhz system clock lvcmos 8ma input buffers spacewire interface pin no. pin name i/o type description b2 rst i lvcmos schmitt rst must remain low for 6 clock cycles before transitioning high, and must transition high 3 clock cycles before valid data. p1 txclk_in_1 i lvcmos clock input 1 to transmitter used to clock lvds output. any phase relationship is allowed between txclk _in & host_clk. p2 txclk_in_2 i lvcmos clock input 2 to transmitter used to clock lvds output. any phase relationship is allowed between txclk_in & host_clk. p4 txclk_in_3 i lvcmos clock input 3 to transmitter used to clock lvds output. any phase relationship is allowed between txclk_in & host_clk. n3 txclk_in_4 i lvcmos clock input 4 to transmitter used to clock lvds output. any phase relationship is allowed between txclk_in & host_clk. t12 tx1_d o hs-lvcmos transmit data for port 1 high speed cmos 12ma i/o buffers t13 txi_s o hs-lvcmos transmit strobe for port 1 r12 rxi_d i hs-lvcmos receive data for port 1 r13 rxi_s i hs-lvcmos receive strobe for port 1 t9 tx2_d o hs-lvcmos transmit data for port 2 t10 tx2_s o hs-lvcmos transmit strobe for port 2 r9 rx2_d i hs-lvcmos receive data for port 2 r10 rx2_s i hs-lvcmos receive strobe for port 2 a9 tx3_d o hs-lvcmos transmit data for port 3 a10 tx3_s o hs-lvcmos transmit strobe for port 3 b9 rx3_d i hs-lvcmos receive data for port 3 b10 rx3_s i hs-lvcmos receive strobe for port 3 a12 tx4_d o hs-lvcmos transmit data for port 4 23 a13 tx4_s o hs-lvcmos transmit strobe for port 4 b12 rx4_d i hs-lvcmos receive data for port 4 b13 rx4_s i hs-lvcmos receive strobe for port 4 m2 l2 k2 j3 h3 tx_div[4:0] i lvcmos initial transmit divide by input. on power up of rst assertion the data set by these pins will be loaded into all 4 of the initialization divide registers. r16 t16 rx1_d_lv+ rx1_d_lv- i lvds port 1 non-inverting receive data input pin port 1 inverting receive data input pin n16 p16 rx1_s_lv+ rx1_s_lv- i lvds port 1 non-inverting receive strobe input pin port 1 inverting recei ve strobe input pin r15 t15 tx1_d_lv+ tx1_d_lv- o lvds port 1 inverting transmit data output pin port 1 non-inverting transmit data output pin n15 p15 tx1_s_lv+ tx1_s_lv- o lvds port 1 non-inverting transmit strobe output pin port 1 inverting transmit strobe output pin l16 m16 rx2_d_lv+ rx2_d_lv- i lvds port 2 non-inverting receive data input pin port 2 inverting receive data input pin j16 k16 rx2_s_lv+ rx2_s_lv- i lvds port 2 non-inverting receive strobe input pin port 2 inverting recei ve strobe input pin l14 m14 tx2_d_lv+ tx2_d_lv- o lvds port 2 non-inverting transmit data output pin port 2 inverting transmit data output pin j14 k14 tx2_s_lv+ tx2_s_lv- o lvds port 2 non-inverting transmit strobe output pin port 2 inverting transmit strobe output pin g16 h16 rx3_d_lv+ rx3_d_lv- i lvds port 3 non-inverting receive data input pin port 3 inverting receive data input pin e16 f16 rx3_s_lv+ rx3_s_lv- i lvds port 3 non-inverting receive strobe input pin port 3 inverting recei ve strobe input pin g14 h14 tx3_d_lv+ tx3_d_lv- o lvds port 3 non-inverting transmit data output pin port 3 inverting transmit data output pin e14 f14 tx3_s_lv+ tx3_s_lv- o lvds port 3 non-inverting transmit strobe output pin port 3 inverting transmit strobe output pin c16 d16 rx4_d_lv+ rx4_d_lv- i lvds port 4 non-inverting receive data input pin port 4 inverting receive data input pin a16 b16 rx4_s_lv+ rx4_s_lv- i lvds port 4 non-inverting receive strobe input pin port 4 inverting recei ve strobe input pin c15 d15 tx4_d_lv+ tx4_d_lv- o lvds port 4 non-inverting transmit data output pin port 4 inverting transmit data output pin a15 b15 tx4_s_lv+ tx4_s_lv- o lvds port 4 non-inverting transmit strobe output pin port 4 inverting transmit strobe output pin spacewire interface pin no. pin name i/o type description 24 j2 lv_cm i lvcmos interface enable used to select lvds i/o or lvcmos time code signal pin no. pin name i/o type description t6 tick_in i lvcmos when asserted and the link inte rface is in the run state the transmitter sends a time-code immediately after the current character has been transmitted. six-bit time input port, a two- bit control flag input port. t7 tick_out o lvcmos will be asserted whenever the lin k interface is in the run state and the receiver receives a valid time-code. a six-bit time output port and a two-bit control flag output port. t2 t3 t4 r2 r3 r4 r5 r6 time_code0 time_code1 time_code2 time_code3 time_code4 time_code5 time_code6 time_code7 i/o lvcmos 8 bit time code port. system interface fifos pin no. pin name i/o type description c1 d1 f1 g1 c2 d2 e2 f2 g2 tx_data0 tx_data1 tx_data2 tx_data3 tx_data4 tx_data5 tx_data6 tx_data7 tx_data8 i lvcmos data inputs for 9-bit bus a3 a4 a6 a7 b3 b4 b5 b6 b7 rx_data0 rx_data1 rx_data2 rx_data3 rx_data4 rx_data5 rx_data6 rx_data7 rx_data8 o lvcmos data outputs for 9-bit bus k1 oe i lvcmos external port output enable l1 csel i lvcmos external chip select input spacewire interface pin no. pin name i/o type description 25 d3 tx_push i lvcmos transmit push signal. one location of data will be loaded in the transmit fifo on the rising edge of host_clk when tx_push is low c4 rx_pop i lvcmos receive pop signal. fifo pop request, active low c5 rx_empty o lvcmos empty flag: when rx_empty is high, the receive fifo is empty. synchronized to host_clk. e3 tx_full o lvcmos full flag: when tx _full is low, the transmit fifo is full. ff is synchronized to host-clk. c6 rx_aempty o lvcmos almost empty: when the rx_a empty is high, the receive fifo is 8 locations from being empty. f3 tx_afull o lvcmos almost full: when the tx_a full is high, the transmit fifo is 8 locations from being full. system interface fifos pin no. pin name i/o type description 26 13.0 operational environment parameter limits units total ionizing dose (tid) >1e5 rads(si) single event latchup (sel) 2 >100 mev-cm 2 /mg seu saturated cross-section 1.1e-6 cm 2 /port onset single event upset (seu) let 3 >28 mev-cm 2 /mg neutron fluence 1e14 n/cm 2 notes: 1. worst case temperature and voltage of t c = +125 o c, v dd = 3.6v, v ddc = 2.7v for sel. 2. worst case test temperature and voltage of t c = +25 o c, v dd = 3.0v, v ddc = 2.5v for seu. 27 14.0 electrical characteristics 14.1 absolute maximum ratings: 1 (referenced to vss) notes: 1.stresses outside the listed absolute maximu m ratings may caught permanent damage to th e device. this is stress rating only, f unctional operation of the device at these or any other conditions beyo nd limits indicated in the operational sections is not recommended. expo sure to absolute maxi mum rating conditions for extended periods may affect device reliability and performance. 2. per mil-std-883, method 1012.1, section 3.4.1, p d = t j (max) -t c (max) ? jc 14.2 recommended operating conditions symbol description limits units v ddc core supply voltage -0.3 to 3.6 v v dd i/o supply voltage -0.3 to 4.3 v v i/o voltage on any pin during operation -0.3 to v dd + 0.3 v i i dc input current + 10 ma p d 2 maximum package power dissipation permitted at t c =105 o c 11 w t stg storage temperature -65 to +150 ? c ? jc thermal resistance, junction to case 4.0 ? c/w t j junction temperature 150 ? c symbol description limits units v ddc core supply voltage 2.3 to 2.7 v v dd i/o supply voltage 3.0 to 3.6 v v in input voltage on any pin 0 to v dd v t c case temperature -40 to +105 ? c t rise input rise time cmos inputs (vil-vih) < 20 ns lvds inputs (vtl-vth) < 20 ns t fall input fall time cmos inputs (vih-vil) < 20 ns lvds inputs (vth-vtl) < 20 ns 28 14.3 dc electrical characteristics - lvds driver (pre and post-radiation) * (v dd = 3.3v + 0.3v; v ddc = 2.5v + 0.2v) unless otherwise noted, tc is per the temperature range ordered notes: *for devices procured with a total ionizi ng dose tolerance guarantee, the post-i rradiation performance is guaranteed at 25 o c per mil-std-883 method 1019, con- dition a, up to the maxi mum tid level procured. 1. current into device pins is defined as positive. current out of device pins is defined as negative. all voltages are referen ced to ground except differential voltages. 2. guaranteed by characterization 3. output short circuit current (ios) is specified as magnitude only, minus sign indicates direction only. 4. capacitance is measured for initial qua lification and when design ch anges may affect the input/output capacitance. capacitan ce is measured between the designated terminal and vss at a frequency of 1mhz and a signal amplitude of 50mv maximum. 5. supplied as a design guideline, not tested or guaranteed. symbol parameter condition min max unit v ol low-level output voltage r l = 100 ? 0.8 --- v v oh 5 high-level output voltage r l = 100 ? --- 2.1 v v od 1,5 differential output voltage r l = 100 ? 250 600 mv ? v od 1 change in magnitude of v od for complementary output states r l = 100 ? --- 35 mv v os 5 offset voltage r l = 100 ? , 1.1 1.8 v ? v os change in magnitude of v os for complementary output states r l = 100 ?? v oh + v ol 2 --- 25 mv i os 2, 3 output short circuit current v out+ = 0v or v dd v out- = 0v or v dd -9.0 9.0 ma i oz output three-st ate current lv_cm = v ss v o = 0v or v dd, v dd = 3.6v -10 +10 ?? c outlvds 4 lvds output capacitance --- 10 pf = v os 29 14.4 dc electrical char acteristics - lvds receiver (pre and post-radiation) * 1 (v dd = 3.3v + 0.3v; v ddc = 2.5v + 0.2v) unless otherwise noted, tc is per the temperature range ordered. notes: *for devices procured with a to tal ionizing dose tolerance guarantee, the pos t-irradiation performance is guaranteed at 25 o c per mil-std-883 method 1019, con- dition a, up to the maximum tid level procured. 1. current into device pins is defined as positive. current out of device pins is defined as negative. all voltages are referen ced to ground. 2. guaranteed by characteriz ation and functionally tested. 3. capacitance is measured for initial qualification and when desi gn changes may affect the inpu t/output capacitance. capacitan ce is measured between the designated terminal and vss at a frequency of 1mhz and a signal amplitude of 50mv maximum. symbol parameter condition min max unit v cmr 2 common mode supply voltage v id = 200mv peak-to-peak 0.1 2.3 v i lvdin receiver input current v in =2.4v -15 +15 ?? i cs cold spare leakage current v in = 3.6v, v dd = v ss -10 +10 ?? v th 2 differential input high threshold vcm = +1.2v v cm +0.1 --- v v tl 2 differential input low threshold vcm = +1.2v --- v cm -0.1 v v cl input clamp voltage i in = + 1.0ma -1.5 -0.4 v c inlvds 3 lvds input capacitance --- 10 pf 30 14.5 dc electrical characteristics - lvcmos i/o (pre and post-radiation)* (v dd = 3.3v + 0.3v; v ddc = 2.5v + 0.2v) unless otherwise noted, tc is per the temperature range ordered. symbol parameter condition min max unit v ih 1 high-level input voltage 0.7v dd --- v v il 1 low-level input voltage --- 0.3v dd v v ol low-level output voltage iol = 8.0ma iol = 12ma iol = 100 ? a --- 0.4 0.4 0.25 v v oh high-level output voltage ioh = -8.0ma ioh = -12ma ioh = -100 ? a v dd -0.6 v dd- 0.6 v dd- 0.25 --- v i cmosin input leakage current v in = v dd or v ss -1 1 ?? v t- rst pin input low threshold --- 1.3 v v t+ rst pin input high threshold 1.65 --- v v h rst pin hysteresis 0.6 --- v i os 3,4 output short circuit current v o = v dd and v ss -100 100 ma i ol12 5 output current (sink) v in = v dd or v ss v ol = 0.4v tx1_d, tx1_s, tx2_d, tx2_s, tx3_d, tx3_s, tx4_d, tx4_s --- 12 ma i oh12 5 output current (souce) v in = v dd or v ss v oh = v dd - 0.6v tx1_d, tx1_s, tx2_d, tx2_s, tx3_d, tx3_s, tx4_d, tx4_s -12 --- ma i ol8 5 output current (sink) v in = v dd or v ss v ol = 0.4v tick_out, rx_data[8:0], rx_empty, tx_full, aemty_flag, afull_flag, time_code[7:0] --- 8ma i oh8 5 output current (source) v in = v dd or v ss v oh = v dd -0.6v tick_out, rx_data[8:0], rx_empty, tx_full, aemty_flag, afull_flag, time_code[7:0] -8 --- ma c incmos 6 input capacitance 15 pf c outcmos 6 output capacitance 15 pf 31 notes *for devices procured with a to tal ionizing dose tolerance guarantee, the pos t-irradiation performance is guaranteed at 25 o c per mil-std-883 method 1019, con- dition a, up to the maximum tid level procured. 1. functional tests are conducted in accordance with mil-std-883 with th e following input test conditions: v ih = v ih (min) + 20%, - 0%; v il = v il (max) + 0%, - 50%, as specified herein, for ttl, cmos, or schmitt compatible in puts. devices may be tested usin g any input voltage within the above specified range, but are guaranteed to v ih (min) and v il (max). 2. per mil-prf-38535, for current density 5.0e5 amps/cm2, the ma ximum product of load capacitance (per output buffer) times fre quency should not exceed 3,765 pf/mhz. 3. supplied as a design limit bu t not guaranteed or tested. 4. not more than one output may be shorted at a time for maximum duration of one second. 5. guaranteed by characterization. 6. capacitance measured for initial qualifica tion and when design changes may affect th e value. capacitance is measured between the designated terminal and v ss at frequency of 1mhz and a signal amplitude of 50mv rms maximum. 32 14.6 dc electrical characteristics - power supply operating characteristics (pre- and post-radiation) * (v dd = 3.3v + 0.3v; v ddc = 2.5v + 0.2v) unless otherwise noted, tc is per the temperature ordered. symbol parameter condition min max unit i ddclv1 active core power supply current one spw port active (lvds) v ddc = 2.7v host_clk = 2.5mhz one txclk_in = 10mhz 60 host_clk = 25mhz one txclk_in = 100mhz 480 ma host_clk = 50mhz one txclk_in = 200mhz 960 i ddclv4 active core power supply current four spw ports active (lvds) v ddc = 2.7v host_clk = 2.5mhz txclk_in[1:4] = 10mhz 75 host_clk = 25mhz txclk_in[1:4] = 100mhz 650 ma host_clk = 50mhz txclk_in[1:4] = 200mhz 1275 i ddlv1 active i/o power supply current one spw port active (lvds) v dd = 3.6v host_clk = 2.5mhz one txclk_in = 10mhz 21 host_clk = 25mhz one txclk_in = 100mhz 26 ma host_clk = 50mhz one txclk_in = 200mhz 29 i ddlv4 active i/o power supply current four spw ports active (lvds) v dd = 3.6v host_clk = 2.5mhz txclk_in[1:4] = 10mhz 30 host_clk = 25mhz txclk_in[1:4] = 100mhz 50 ma host_clk = 50mhz txclk_in[1:4] = 200mhz 60 i ddcs standby core power supply current v ddc =2.7v host_clk=0mhz txclk_in1=0mhz txclk_in2=0mhz txclk_in3=0mhz txclk_in4=0mhz room/cold 200 ? a hot 12 ma 33 * for devices procured with total ionizing dose tolerance guarantee, the post-radiation performance is guaranteed at 25 o c per mil-std-883 me thod 1019 , condition a up to the maximum tid level procured. symbol parameter condition min max unit i dds standby i/o power supply current v dd = 3.6v host_clk = 0mhz, txclk_in1 = 0mhz, txclk2_in = 0mhz, txclk_in3 = 0mhz, txclk_in4 = 0mhz 20 m ? i ddccm1 active core power supply current one spw port active (lvcmos) v ddc = 2.7v host_clk = 2.5mhz one txclk_in = 10mhz 60 host_clk = 25mhz one txclk_in = 100mhz 480 ma host_clk = 50mhz one txclk_in = 200mhz 960 i ddccm4 active core power supply current four spw ports active (lvcmos) v ddc = 2.7v host_clk = 2.5mhz txclk_in[1.4] = 10mhz 74 host_clk = 25mhz txclk_in[1.4] = 100mhz 650 ma host_clk = 50mhz txclk_in[1.4] = 200mhz 1275 i ddcm1 active i/o power supply current one spw port active (lvcmos) v dd = 3.6v host_clk = 2.5mhz one txclk_in = 10mhz 20 host_clk = 25mhz one txclk_in = 100mhz 35 ma host_clk = 50mhz one txclk_in = 200mhz 45 i ddcm4 active i/o power supply current four spw ports active (lvcmos) v dd = 3.6v host_clk = 2.5mhz txclk_in[1.4] = 10mhz 22 host_clk = 25mhz txclk_in[1.4] = 100mhz 60 ma host_clk = 50mhz txclk_in[1.4] = 200mhz 110 34 14.7 ac electrical ch aracteristics - power se quencing and reset * (v dd = 3.3v + 0.3v; v ddc = 2.5v+ 0.2v) unless otherwise noted, t c is per the temperature ordered. * for devices procured with total ionizi ng dose tolerance guarantee, the post-radiatio n performance is guaranteed at 25 o c per mil-std-883 me thod 1019, condition a up to the maximum tid level procured. 1. guaranteed by design. symbol parameter condition min max unit t vcd 1 v dd valid to v ddc delay v dd > 3.0v; v ddc > 2.25v 0 - ns t drst 1 minimum number of full clock cycles (host_clk) between rising edge of rst and inputs valid - 3 - host_clk t crst 1 minimum number of full clock cycles (host_clk) that rst must remain low before rst can transition high - 6 - host_clk 35 figure 18. power sequencing and reset timing diagram figure 19. reset timing diagram 36 14.8 ac electrical characteristics - lvds transmit port 1,2 * (v dd = 3.3v + 0.3v; v ddc = 2.5v + 0.2v) unless otherwise noted, tc is per the temperature ordered notes: *for devices procured with total ionizing dose tolerance guarantee, the post-radiation performance is guaranteed at 25 o c per mil-std-883 me thod 1019 , condition a up to the maximum tid level procured. 1. generator waveform for all tests unless otherwise sp ecified: f =1 mhz, zo = 50, tr < 1ns, and tf < 1ns. 2. c l includes probe and jig capacitance. 3. guaranteed by characterization. 4. guaranteed by design. symbol parameter min max unit t skdd differential skew --- 500 ps t rised 4 rise time --- 2.2 ns t falld 4 fall time --- 2.2 ns t dsskewlv lvds data/strobe output skew (per port) --- 1 ns figure 20. lvds driver differential skew, rise and fall time test circuit 37 figure 21. lvds driver tskdd timing diagram figure 22. lvds driver ri se and fall timing diagra m 38 figure 23. lvds driver data/strobe output skew 39 figure 25. lvds receive port minimum data/strobe separation vddio 40pf vddio dut 14.9 ac electrical characteristics - lvds receiver port 1, 2* (v dd = 3.3v + 0.3v; v ddc = 2.5v + 0.2v) unless otherwise noted, tc is per the temperature ordered. notes: *for devices procured with total ionizing dose tolerance guarantee, the post-radiation pe rformance is guaranteed at 25 o c per mil-std-883 me thod 1019 , condition a up to the maximum tid level procured. 1. generator waveform for all tests unless otherwise sp ecified: f =1 mhz, zo = 50, tr < 1ns, and tf < 1ns. 2. c l includes probe and jig capacitance. symbol parameter min max unit t dssep minimum data/strobe separation (per port) 3.5 --- ns figure 24. lvds receiver equivalent test circuit 100 ? 100 ? figure 26. cmos equivalent test load 40 14.10 ac electrical characteristics - lvcmos spw transmit port * (v dd = 3.3v + 0.3v; v ddc = 2.5v + 0.2v) unless otherwise noted, tc is per the temperature ordered. notes: *for devices procured with total ionizi ng dose tolerance guarantee, the post-ra diation performance is guaranteed at 25 o c per mil-std-883 method 1019, condition a up to the maximum tid level procured. 1. guaranteed by design. 14.11 ac electrical char acteristics - lvcmos spw receive port* (v dd = 3.3v + 0.3v; v ddc = 2.5v + 0.2v) unless otherwise noted, tc is per the temperature ordered. notes: *for devices procured with total ionizi ng dose tolerance guarantee, the post-ra diation performance is guaranteed at 25 o c per mil-std-883 method 1019, condition a up to the maximum tid level procured. symbol parameter min max unit t dsskewcm data/strobe output skew (per port) --- 1.5 ns t tlhcm 1 lvcmos spw transmit out put rise time --- 2.4 ns t thlcm 1 lvcmos spw transmit output fall time --- 1.3 ns symbol parameter min max unit t dssepcm minimum data/strobe separation (per port) 3.5 ns figure 27. lvcmos transmit port data/strobe output skew figure 28. lvcmos receive port minimum data/strobe separation tdskewcm 41 14.12 ac electrical characteristics - host clock and spw input clocks * (v dd = 3.3v + 0.3v; v ddc = 2.5v + 0.2v) unless otherwise noted, tc is per the temperature ordered. notes: *for devices procured with total ionizi ng dose tolerance guarantee, the post-r adiation performance is guaranteed at 25 o c per mil-std-883 method 1019, condition a up to the maximum tid level procured. 1. host_clk must run at 0.25x the fastest txclk_in frequency. symbol parameter min max unit f host 1 host_clk frequency 2.5 50 mhz f txclkin spacewire ports input clock freque ncies txclk_in_1, txclk_in_2, txclk_in_3, and txclk_in_4 10 200 mhz figure 29. host_clk max txclk_in requirements 42 14.13 ac electrical ch aracteristics - time code interface * (v dd = 3.3v + 0.3v; v ddc = 2.5v + 0.2v) unless otherwise noted, tc is per the temperature ordered. notes: *for devices procured with total ionizing dose tolerance guarantee, the post-radiation performance is guaranteed at 25 o c per mil-std-883 me thod 1019 , condition a up to the maximum tid level procured. 1. guaranteed by design. 2. time code signals time-code6 and time-code7 are excluded. symbol parameter min max unit t tcds 2 time code data setup time to host_clk rising edge and tick_in high 2--- ns t tcdh 2 time code data hold time from host_clk rising edge and tick_in high 0--- ns t tis tick_in setup time to host_c lk rising edge and time_code va l i d 2.5 --- ns t tih tick_in hold time from host_clk rising edge and time_code va l i d 0--- ns t tcv 2 time from host_clk rising edge to time_code valid --- 15 ns t thvh time from host_clk rising edge to tick_out high 3 15 ns t thvl time from host_clk rising edge to tick_out low 3 15 ns t tohl 1,2 tick_out high to low (host_clk) --- 1.5 ns t tolh 1,2 tick_out low to high (host_clk) --- 1.5 ns figure 30. tick_in the tick_in signal requests the transmission of a time code. the 8-bit time_code port se nds the time code value. when the route r is in the run state and tick_in is asserted, the router will send a time-code immediately after the character currently being transmitted has finished. 43 figure 31. tick_out interface tick_out signals that a time code has arrived at a spacewire interface. tick_out is asserted whenever the link interface is in the run state and the receiver receives a valid time code. the 8-bit time code port time_code[7:0] will reflect the current value of the time cod e. a valid time code is a time code that is one more than th e current value of the router's time-counter. 44 14.14 ac electrical characteristics - transmit fifo * (v dd = 3.3v + 0.3v; v ddc = 2.5v + 0.2v) unless otherwise noted, tc is per the temperature ordered. notes: *for devices procured with total ionizing dose tolerance guarantee, the post-radiation performance is guaranteed at 25 o c per mil-std-883 me thod 1019 , condition a up to the maximum tid level procured. 1. guaranteed by design. symbol parameter min max unit t txs transmit data setup time to host_clk rising edge (tx_push and c se l valid low) 3--- ns t txh transmit data hold time from host_clk rising edge (tx_push and c se l valid low) 0--- ns t txpushs transmit push setup time to host_clk rising edge and csel low 6--- ns t txpushh transmit push hold time from host_clk rising edge and csel low 0--- ns t cspushs chip selectsetup time to host_clk rising edge and tx_push low 12 --- ns t cspushh chip select hold time from host_clk rising edge and tx_push low 0--- ns t alm2full 1 almost full to full flag 8 --- # pushes t txaf time from last transmit push to tx_afull --- 9.5 ns t txf time from last transmit push to tx_full --- 9.5 ns figure 32. transmit fifo almost full bag 45 note: this figure is for illustrative purposes. max throughput on sy stem port is 200mbps. figure 33.transmit port push figure 34.transmit port push with chip select transition 46 14.15 ac electrical characteristics - receive fifo * (v dd = 3.3v + 0.3v; v ddc = 2.5v + 0.2v)unless otherwise noted, tc is per the temperature ordered. notes: *for devices procured with total ionizing dose tolerance guarantee, the post-radiation performance is guaranteed at 25 o c per mil-std-883 me thod 1019 , condition a up to the maximum tid level procured. 1. guaranteed by design. symbol parameter min max unit t rxh receive data hold time from host_clk rising edge (r x_pop and csel valid low) 3--- ns t rxpops receive pop setup time to host_clkrising edge and csel low 3--- ns t rxpoph receive pop hold time from host_clk rising edge and csel low 0--- ns t cspops chip select setup time to host_clk rising edge and rx_pop low 13 --- ns t cspoph chip select hold time from host_clk rising edge and rx_pop low 0 --- ns t alm2emy 1 almost empty flag to empty flag 8 --- # pops t rxae time from last receive data pop to rx_aempty --- 9.5 ns t rxe time from last receive data pop to rx_empty high --- 9.5 ns figure 35. receive fifo almost empty flag 47 figure 36. receive port pop system port read timing specification, reading data out of system port fifo 48 14.16 ac electrical chara cteristics - control inputs and reset * (v dd = 3.3v + 0.3v; v ddc = 2.5v + 0.2v) unless otherwise noted, tc is per the temperature ordered. notes: *for devices procured with total ionizing dose tolerance guarantee, the post-radiation performance is guaranteed at 25 o c per mil-std-883 me thod 1019 , condition a up to the maximum tid level procured. symbol parameter min max unit t rxoe time from oe low to valid output data (see table 16) --- 10 ns t rxcs time from csel low to valid output data (see table 16) --- 10 ns t rxoez time from oe high to tri-state (see table 16) --- 10 ns t rxcsz time from csel high to tri-state (see table 16) --- 10 ns figure 37. control inputs timing information 49 15.0 packaging figure 38. 255-ccga 50 figure 39. 255-cbga 51 figure 40. 255-clga 52 ordering information ut200spw4rtr 4-port spacewire router: ut200spw 4rtr * - lead finish: (note 1) (a) = hot solder dipped or tinned (c) = gold screening: (notes 2 & 3) (p) = prototype flow (temperature range: 25 o c only) (e) = hirel flow (temperature range: -40 ? c to +105 ? c) package type: (z) = 255-lead ceramic land grid array (clga) (s) = 255-lead ceramic column grid array (ccga) (c) = 255-lead ceramic ball grid array (cbga) tid tolerance: (-) = none device type: (4rtr) =4-port spacewire router device type: generic ut200spw spacewire base part number notes: 1. lead finish (a or c) must be specified according to the table below. 2. prototype flow per aeroflex colorado spri ngs manufacturing flows document. tested at 25 ? c only. radiation neither tested nor guaranteed. 3. hirel flow per aeroflex colorado springs manufacturing fl ows document. radiation neith er tested nor guaranteed. package option associated lead finish (z) 255 clga (c) gold (s) 255 ccga (a) hot solder dipped (c) 255 cbga (a) hot solder dipped ** * 53 4-port spacewire router: smd 5962 * _ 08244 * ** * * * * ** * lead finish: (note 1) (c) = gold case outline: (note 2) (x) = 255-lead ceramic land grid array class designator: (q) = qml class q (pending, contact factory for availability) (v) = qml class v (pending, contact factory for availability) device type (01) = ut200spw4rtr (temperature range -40 o c to +105 o c) drawing number: 08244 total dose (r) = 1e5 rad(si) federal stock class designator: no options notes: 1. lead finish is "c" (gold) only. 2. using an altered item drawing (aid), ae roflex offers column attachment as an ad ditional service for the ceramic land grid ar ray (case outline x). if needed, please ask for column attachment when submitting your re quest for quotation. 54 colorado toll free: 800-645-8862 fax: 719-594-8468 se and mid-atlantic tel: 321-951-4164 fax: 321-951-4254 international tel: 805-778-9229 fax: 805-778-1980 west coast tel: 949-362-2260 fax: 949-362-2266 northeast tel: 603-888-3975 fax: 603-888-4585 central tel: 719-594-8017 fax: 719-594-8468 www.aeroflex.com info-ams@aeroflex.com our passion for performance is defined by three attributes represented by these three icons: solution-minded, performance-driven and customer-focused aeroflex colorado springs, inc., reserves the right to make changes to any products and services herein at any time without notice. consult aeroflex or an authorized sales representative to verify that the information in this data sheet is current before using this product. aeroflex does not assume any responsibility or liability arising out of the application or use of any product or service described herein, except as expressly agreed to in writing by aeroflex; nor does the purchase, lease, or use of a pr oduct or service from aeroflex convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual rights of aeroflex or of third parties. aeroflex colorado springs - datasheet definition advanced datasheet - product in development preliminary datasheet - shipping prototype datasheet - shipping qml & reduced hi-rel |
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